1. Field
Exemplary embodiments of the present invention relate to a semiconductor designing technology, and more particularly, to a semiconductor device including a Delay Locked Loop (DLL) and a semiconductor system including the semiconductor device.
2. Description of the Related Art
A clock is generally used as a reference for tuning timing for an operation in a system or a circuit. Also, a clock may be used to secure a fast operation being performed without an error. When an external clock is inputted from an external device and used in an internal circuit, time delay (which is called ‘skew’) is caused by the internal circuit. Herein, a Delay Locked Loop (DLL) is used to compensate for the time delay and make an internal clock have the same phase as the external clock.
Meanwhile, the delay locked loop has an advantage in that it is less affected by noise than a phase locked loop (PLL), which has been used conventionally. For this reason, the delay locked loop is widely used for synchronous semiconductor memories, such as a Synchronous Dynamic Random Access Memory (SDRAM) and a Double Data Rate SDRAM (DDR SDRAM).
The delay locked loop may operate to compensate for a delay time difference between an external clock, i.e., a reference clock signal, and a feedback clock signal obtained as the reference clock signal passes through a replica.
However, as a frequency of the reference clock signal increases, a locking time of the delay locked loop, which is the time taken until a rising edge of the feedback clock signal and a rising edge of the reference clock signal coincides with each other, becomes considerably long. As a result, the delay locked loop does not obtain sufficient timing margin and accordingly, an operation stability of a system including a semiconductor memory device provided with the delay locked loop is deteriorated.